
IDT82V3202
EBU WAN PLL
Electrical Specifications
102
September 11, 2009
8.4
JITTER & WANDER PERFORMANCE
Table 42: Output Clock Jitter Generation
Test Definition 1
Peak to Peak
Typ
RMS
Typ
Note
Test Filter
N x 2.048MHz without APLL
<2 ns
<200 ps
20 Hz - 100 kHz
N x 2.048MHz with T0/T4 APLL
<1 ns
<100 ps
20 Hz - 100 kHz
N x 1.544 MHz without APLL
<2 ns
<200 ps
10 Hz - 40 kHz
N x 1.544 MHz with T0/T4 APLL
<1 ns
<100 ps
10 Hz - 40 kHz
44.736 MHz with T0/T4 APLL
<1 ns
<100 ps
44.736 MHz without APLL
<2 ns
<200 ps
100 Hz - 800 kHz
34.368 MHz with T0/T4 APLL
<1 ns
<100 ps
10 Hz - 400 kHz
34.368 MHz without APLL
<2 ns
<200 ps
10 Hz - 400 kHz
OC-3
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz output
0.004 UI p-p 0.001 UI RMS
GR-253, G.813 Option 2
limit 0.1 UI p-p
(1 UI-6430 ps)
12 kHz - 1.3 MHz
0.004 UI p-p 0.001 UI RMS
G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-6430 ps)
500 Hz - 1.3 MHz
0.001 UI p-p 0.001 UI RMS
G.813 Option 1
limit 0.1 UI p-p
(1 UI-6430 ps)
65 kHz - 1.3 MHz
OC-12
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical
transceiver)
0.018 UI p-p 0.007 UI RMS
GR-253, G.813 Option 2
limit 0.1 UI p-p
(1 UI-1608 ps)
12 kHz - 5 MHz
0.028 UI p-p 0.009 UI RMS
G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-1608 ps)
1 kHz - 5 MHz
0.002 UI p-p 0.001 UI RMS
G.813 Option 1, G.812
limit 0.1 UI p-p
(1 UI-160 8ps)
250 kHz - 5 MHz
STM-16
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92
MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical
transceiver)
0.162 UI p-p 0.03 UI RMS
G.813 Option 1, G.812
limit 0.5 UI p-p
(1 UI-402 ps)
5 kHz - 20 MHz
0.01 UI p-p 0.009 UI RMS
G.813 Option 1, G.812
limit 0.1 UI p-p
(1 UI-402 ps)
1 MHz - 20 MHz
Note:
1. CMAC E2747 TCXO is used.